Verilog Ams Vs Verilog Assignment

Contribution¶

A contribution statement is used to give values to continuous signals, in particular to branch potentials or flows:

This statement says that the voltage on the branch named ‘res’ should be driven so that the voltage on the branch should equal r multiplied by the current through the branch.

Contributions may be either explicit, as above, or implicit. Implicit contributions have the target on both sides of the contribution operator. For example:

This implements the series combination of a resistor and a capacitor.

Implicit contributions to branch flows can be used to easily create series combinations whereas implicit contributions to branch potentials can be used to create parallel combinations. For example, the following creates the parallel combination of an inductor and a conductor:

Multiple contributions to the same branch in the same analog process accumulate. For example:

This is equivalent to:

Multiple contributions to a branch flow can be viewed as creating multiple parallel branches. For example, the above example is equivalent to the parallel combination of the output of a controlled current source, a conductor, and a capacitor. Similarly, multiple contributions to a branch potential can be viewed as creating multiple series branches.

The target (left side) must be a branch signal: an access function applied to a continuous branch. The branch may be a named (or explicit) branch, or it may be an unnamed (or implicit) branch, which are given as a single net or a pair of nets. When an implicit branch is given as a pair of nets, the branch is assumed to connect the two nets. When an implicit branch is specified as a single net, the branch is assumed to connect that net to ground.

Here is a resistor module that uses a explicitly declared or named branch:

Here is a resistor module that uses a implicitly declared or unnamed branch:

Descriptions that employ unnamed branches are a little more compact, but also the formulation of the branches is constrained (multiple contributions to flows give a shunt toplogy and to potentials gives a series topology). For this reason people use unnamed branches with the branch topology is simple, and switch to named branches for the more complicated topologies.

The actual contributions occur after the analog block has been evaluated, meaning that the branch values do not change between statements in the analog block. As such, so as long as the values of the right-hand side expressions are not affected, the order of the contribution statements is inconsequential. So for example, these two analog blocks are equivalent:

analog begin V(res) <+ r * I(res); end
analog begin I(cap) <+ c * ddt(V(cap) - r*I(cap)); end
analog begin V(ind) <+ l * ddt(I(ind) - g*V(ind)); end
analog begin I(out) <+ gm * V(in); I(out) <+ g * V(out); I(out) <+ c * ddt(V(out)); end
analog I(out) <+ gm * V(in) + g * V(out) + c * ddt(V(out));
module resistor (p, n); parameter real r = 0; branch (p, n) res; analog V(res) <+ r*I(res); endmodule
module resistor (p, n); parameter real r = 0; analog V(p,n) <+ r*I(p,n); endmodule
analog begin V(in) <+ 200m; V(out) <+ 5*V(in); end analog begin V(out) <+ 5*V(in); V(in) <+ 200m; end

Indirect Assignment¶

An indirect assignment is an alternative to the contribution statement. It also drives a particular branch potential or flow so that a given equation is satisfied, but in this case the driven branch potential or flow need not be in the specified equation. This feature is rarely needed, however it occasionally allows you to describe a component that would cumbersome to describe with contributions. For example, it is possible to describe an ideal opamp using:

This can be read as ‘drive V(out) such that V(pin,nin) == 0’.

The left side of the equation must be either a branch potential or flow, the right side is an expression. The equation may be implicit or explicit.

The driven branch must not also be a target of a contribution statement.

analog begin: V(out): V(pin,nin) == 0; end

Assignment¶

A assignment evaluates the expression on its right hand side and then immediately assigns the value to the variable on its left hand side:

The target (left side) of an analog assignment statement may only be a integer or real variable. It may not be signal or a wire.

Contribution versus Assignment¶

For people new to Verilog-A and Verilog-AMS, contribution and assignment seem to be doing very similar things, and this can confuse them. Here the differences between contribution and assignment are highlighted.

AttributeContributionAssignment
Symbol<+=
Operates onbranch signalsvariables
Actionaccumulatesoverrides
Order dependentnoyes
Evaluatesafter all processesimmediately
Formulationimplicit or explicitexplicit only

In my current role as a design verification engineer, I’m learning Verilog-AMS. I decided to make some notes as I go as a reference for myself. There may be errors in this document; I’m not a Verilog expert. This is just what I’ve gleaned from various online sources.

begin…end Block

Instead of using curly braces (these things: {}) to denote blocks like C/C++ does, Verilog uses the keywords “begin” and “end”.

Procedural Blocks (initial, always, analog)

These three blocks let you do things in-order instead of all-at-once. Outside of these blocks, actions are concurrent. Inside these blocks, actions can be concurrent if certain operators are used but are typically processed one at a time.

You can have multiple and blocks in a module, but you can only have one block in a module. All blocks start execution at the same time. blocks only run once. blocks loop forever (like a block in C/C++). blocks work like blocks, except they can contain analog statements. Non-analog statements should be placed in blocks if possible because this will make the simulation run faster.

Ports

In Verilog, ports are either or , and that’s it. Everything is digital. In Verilog-AMS, digital ports are defined as , and analog ports are defined as .

Numbers

Numbers follow the format . is the number of bits. is either for decimal, for binary, for octal, or for hexadecimal. is the number itself. Example: . Underscores are ignored in numbers.

Parameters and Variables

I don’t know what the keyword means. I think it allows you to assign a value to the variable in the same line. Or maybe it makes the variable a constant. Not sure.

Variables types can be or . variables can have decimal parts. The size of a variable can be set like this: .

Events?

I’m not sure what these are really called. They have the syntax . can be , , or omitted. If it’s omitted, the event will trigger on any change to the signal. The can be either a single statement or a block. A special case of the event syntax is . The in the sensitivity list lets the compiler analyze the statement and pull out any signals that will cause the output of the statement to change. (If signals and cause the output to change, then the compiler will make the sensitivity list .

Assignments

There are several ways to assign signals/parameters to each other. is a blocking assignment and can only be used in a procedural block. It completes the assignment before the next statement is allowed to execute. This means that is equivalent to . is a non-blocking assignment. The code is valid and swaps the values of and . In analog blocks, the assignment operator is used to transfer analog values.

transition() Function

The transition function is explained well in the “Transition filter” section of the “Verilog-AMS Language Reference Manual” by the Designer’s Guide. The function should be used whenever the output of an analog block is changed: . This removes discontinuities and makes it more likely that the simulation will converge.

Sample Programs

It’s always nice to have a few sample programs to refer to. I’m not sure if these programs actually compile, but their syntax looks correct.

Sample Program #1: 4-Bit DAC

The first sample program is a 4-bit digital-to-analog converter from the Wikipedia article on Verilog-AMS.

Sample Program #2: 4-Bit ADC

The second sample program is a 4-bit analog-to-digital converter from the Wikipedia article on Verilog-AMS.

Sample Program #3: AND Gate

The third sample program is a simple AND gate from Andrew Tuline’s “An Introduction to Verilog”.

Photo by Yuri Samoilov

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